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Build this single-sided Xilinx CPLD board at home and experiment with CPLDs and hardware description language (HDL). The source files for the project are in open source KiCad format so you can modify the circuit diagram and PCB if needed. Follow the VHDL CPLD course and learn to program a CPLD using VHDL code.
See a short video of the board on YouTube.
The Xilinx CPLD board has the following features:
The CPLD used in the design is a XC9536XL CPLD from Xilinx. This CPLD is powered from 3.3V. Xilinx do have 5V CPLDs, but these are usually much more expensive than the 3.3V CPLD range. The circuit is powered entirely from 3.3V.
The AVR microcontroller has been added primarily to provide a clock source for the CPLD. Normally a 3.3V oscillator in a SMT package would be used for a clock source, but this is a more specialised part and to keep the design through-hole, it was decided to use the AVR.
In order to fit the circuit to a single-sided PCB, a number of links were used on the board. These links have been added to the circuit as 0Ω resistors (zero ohm resistors). If you don't want to buy 0Ω resistors you can just use a wire link in their place.
All of the parts used in the construction of the CPLD evaluation board are shown in the table below.
Note that crystal X1 and capacitors C7 and C8 are optional. They will only be needed if you would like to provide a more accurate clock signal to the CPLD or need a specific clock for some of the functions on the AVR.
|5||0Ω||R10, R11, R12, R13, R24||Zero ohm resistors in 1/4W resistor package, or wire links||Resistors|
|8||330Ω||R1, R2, R3, R4, R5, R6, R7, R8||1/4W 5% or better|
|10||4k7||R14, R15, R16, R17, R18, R19, R20, R21, R22, R23||1/4W 5% or better|
|1||10k||R9||1/4W 5% or better|
|1||4k7||RR1||9-pin 8 resistor network, SIP package|
|2||22p||C7, C8||Ceramic capacitors. Optional.||Capacitor|
|5||100n||C1, C2, C3, C5, C6||X7R capacitors|
|1||10μF||C4||Electrolytic Capacitor, 10v or more|
|8||3mm LED||D1, D2, D3, D4, D5, D6, D7, D8||3mm through-hole red LEDs||Semiconductor|
|1||ATtiny2313-20PU||IC1||Atmel AVR microcontroller in 20 pin DIP package|
|1||XC9536XLPC44||U1||Xilinx CPLD in 44 pin PLCC package|
|1||20 pin DIP socket||IC1||20 pin DIP socket for the AVR microcontroller||IC sockets|
|1||PLCC 44 socket||U1||44 pin PLCC socket for the CPLD|
|1||Crystal||X1||Optional Crystal for the AVR||Crystal|
|1||7 × 2 IDC male header||P1||7 × 2 IDC male header, 2.54mm spaced pins||Connectors|
|1||2 pole PCB terminal||P2||PCB screw terminal connector|
|1||3 × 2 pin header||P3||3 × 2 pin header, 2.54mm spaced pins|
|2||5 pin socket||P4, P5||5 pin female socket, 2.54mm spacing|
|1||12 pin socket||P6||12 pin female socket, 2.54mm spacing|
|1||6 pin socket||P7||6 pin female socket, 2.54mm spacing|
|1||8 pin socket||P8||8 pin female socket, 2.54mm spacing|
|1||Push button switch||SW1||6mm × 6mm tactile push-button PCB mount switch||Switches|
|1||8 DIP switch package||SW2||8 switches in a DIP package. Can solder a 16 pin IC socket into the board to insert the switch package into.|
Download the KiCad source files for the CPLD evaluation board. The download contains the source files for the KiCad project with circuit diagram and PCB layout.
When making the PCB using the toner transfer method, be extra careful when ironing the PCB image to the board as it is a bigger board. Make sure that the whole area of the board is ironed sufficiently.
Solder the zero ohm resistors or wire links to the board first. I would suggest soldering the rest of the resistors to the board after this as it will be easier to solder these low-height components before other higher components are added.
Solder the 44 pin PLCC CPLD socket to the board (U1), the power connector P2, Xilinx CPLD JTAG header P1 and some of the capacitors (e.g. C1, C4, C5) to the board. Insert the XC9536XL CPLD into the PLCC socket.
It is now possible to test the CPLD by programming it. In order to perform this test, you will need a 3.3V power supply and a JTAG programmer that works with Xilinx CPLDs.
Solder the 20 pin DIP socket for the ATtiny2313 (IC1), the AVR ISP header P3 and capacitor C6. Test that the AVR microcontroller can be "seen" by the programming software and AVR programmer.
After testing the CPLD and AVR, the rest of the components can be soldered to the board to finish it. Leave off the crystal X1 and capacitors C7 and C8 for now. Place has been made for the crystal and the supporting capacitors should a more accurate clock be required.
The Xilinx ISE WebPACK software can be used to program the CPLD for testing purposes.
Atmel Studio and an AVR programmer can be used to program the ATtiny2313 microcontroller for testing purposes.
After the LEDs, switch bank and supporting resistors have been soldered to the board, the board can be tested further by writing VHDL code to connect the switches to the LEDs as explained in the article on starting a new Xilinx CPLD project in ISE.
You may also like to follow the CPLD VHDL course which makes use of this CPLD board to teach VHDL.
This test routes AVR pin PB4 to one of the CPLD board LEDs using VHDL code. A program is then loaded to the AVR that will produce a very slow clock pulse on AVR pin PB4 which flashes the LED on and off.
On the CPLD board, the ATtiny2313 PB4 pin (pin 16) is wired to CPLD pin P7. This is the pin that the AVR will put the clock pulse on.
LED D1 is the LED that is flashed on and off. It is wired to pin P36 of the CPLD.
First load the CPLD configuration file to the CPLD that connects CPLD pin P7 to CPLD pin P36 (this connects AVR pin PB4 to the LED on CPLD pin P36).
VHDL, UCF and JED files: CPLD_clk_LED_test.zip (5.8kB)
Program the AVR next which will start the LED on the board flashing on and off.
Atmel Studio project with source code: AVR_CPLD_clk_test.zip (14.4kB)