Created on: 22 November 2012
This article shows how to make a new project using the Xilinx ISE software. A VHDL project for configuring a Xilinx CPLD is created.
The example simply connects inputs (a bank of 8 switches interfaced to CPLD pins) to outputs (8 LEDs interfaced to CPLD pins) within the CPLD. The example uses the home built CPLD board which contains a XC9536XL CPLD and the home built parallel cable. The software used in this project is Xilinx ISE WebPACK Design Suite 14.2 running on Windows 7.
Either start the software from the desktop icon or find it on the Windows menu as shown in this image:
Start a new project by clicking the New Project... button as shown below or by clicking File → New Project... This will open the New Project Wizard dialog box.
Select the desired location of the new project and then fill in the name of the new project as shown below.
Fill in the project settings for the device and language to be used. If using the home built CPLD board, then select the XC9536XL device. Choose VHDL as the preferred language for this example.
See below for information on how to select the Speed parameter.
The speed grade can be found on the CPLD package as shown below, which shows a CPLD with a speed grade of 7 (hence -7 is selected in the dialog box).
The smaller the speed grade number, the faster the CPLD – e.g. a CPLD with a speed grade of 7 has a 7.5ns pin-to-pin delay, and a CPLD with a speed grade of 5 has a 5ns pin-to-pin delay.
Click Next button and you will be shown a summary of the project settings. Click the Finish button.
We now need to add a VHDL source file to the project and then add the VHDL code to the file that will connect the switches on the CPLD to the LEDS.
Click Project → New Source... to open the New Source Wizard dialog box.
Click "VHDL Module" and then type the desired file name as shown here:
Click the Next button.
Fill in the ports for the module as shown below. This defines a bus of 8 switches called SW and a bus of 8 LEDs called LED.
This step could also be skipped and the ports defined in the VHDL file manually.
Click the Next button and a summary of the new source file will be shown. Click the Finish button.
The new source file that you created will now be displayed in the ISE Project Navigator. Add the following line of VHDL code between the begin and end keywords:
LED <= SW;
Your VHDL source code in the project navigator should now look like this:
This line of VHDL connects the switches on the CPLD to the LEDs one-to-one. It is possible to do this in one statement as the LEDs and switches were defined as buses.
Save the file after you have added the line of VHDL code.
A UCF (user constraints file) must now be added to the project. This file will map the physical pins of the CPLD to the pin names used in the VHDL code.
The pin numbers can be obtained from the CPLD board circuit diagram. The mapping of the CPLD pins to the switches and LEDs for the home built CPLD board are shown below.
NET "LED<0>" LOC = "P36" ; NET "LED<1>" LOC = "P35" ; NET "LED<2>" LOC = "P34" ; NET "LED<3>" LOC = "P33" ; NET "LED<4>" LOC = "P29" ; NET "LED<5>" LOC = "P28" ; NET "LED<6>" LOC = "P27" ; NET "LED<7>" LOC = "P26" ; NET "SW<0>" LOC = "P44" ; NET "SW<1>" LOC = "P1" ; NET "SW<2>" LOC = "P42" ; NET "SW<3>" LOC = "P43" ; NET "SW<4>" LOC = "P40" ; NET "SW<5>" LOC = "P39" ; NET "SW<6>" LOC = "P38" ; NET "SW<7>" LOC = "P37" ;
LED<x> is an individual line of the 8-bit LED bus. The numbers starting with "P" are the physical pin numbers on the CPLD package.
So the first line in this listing says: "Map LED 0 of the 8-bit LED bus to pin 36 of the CPLD".
Click Project → New Source... as shown below.
Click Implementation Constraints File and type a file name in the New Source Wizard dialog box.
Click Next and then Finish.
User constraints must now be added to the UCF file just created.
Click the '+' sign next to the VHDL file to display the UCF file, then right-click the UCF file and click Open on the menu that pops up as shown below. This should open the UCF file in the Xilinx PACE application.
If the file does not open in Xilinx PACE, then you need to change the settings: click Edit → Preferences... from the top menu. In the dialog box that pops up, click Editors under ISE General. Now click the PlanAhead (FPGA) / Pace (CPLD) radio button. Click the OK button to finish.
In the Pace application program, enter the pin numbers for the switches and LEDs as listed above and shown below. Save the file and then close Pace when done.
The next step is to generate a file that can be loaded to the CPLD to implement the VHDL code.
Make sure that the VHDL file is selected under "Hierarchy" in the top left pane of ISE. Click the '+' sign next to Implement Design and then Configure Target Device. Right-click Manage Configuration Project (iMPACT) and then click Run on the menu that pops up as shown below.
The Translate, Fit and Generate Programming File steps will complete and then the iMPACT application will start.
Plug the programmer (e.g. the Xilinx Parallel JTAG Cable) into the PC and into the target CPLD board. Switch the power to the CPLD board on.
In iMPACT, click the "Launch Wizard" icon on the top toolbar as shown below. Now click the OK button and the programmer and CPLD should automatically be detected.
You will now be prompted to assign a configuration file to the CPLD. Click Yes in the dialog box.
Now select the JED file for the project. Make sure that you navigate to the correct project.
Click "OK" in the next dialog box to accept the device programming properties.
Right-click the CPLD image and then click Program on the menu that pops up. The CPLD will now be programmed with the configuration file that was assigned to it.
After loading the configuration file for your project, switching the switches on the DIP switch bank should switch LEDs on from the array of 8 LEDs. One switch on the switch bank should switch on one LED, each switch is connected to a single LED.
If your project does not work as it is supposed to, then try check or try the following:
Download the complete project for ISE 14.2: in8_out8.zip (699.8kB)
Download just the VHDL, UCF and JED files from the above project: CPLD_eval_brd_src.zip (5.9kB)