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Tutorial 9: S-R Latch in VHDL

Created on: 16 January 2013

In this tutorial, a S-R latch is designed and written in VHDL, it is then implemented on a Xilinx CPLD.

This video shows the VHDL S-R latch operating.

Can't see the video? View on YouTube →

S-R Latch Operation

An S-R latch (set-reset latch) made from two NOR gates is shown below. This latch has active high inputs.

S-R latch made from NOR gates, active high inputs

S-R Latch, Active High Inputs


The S-R latch is implemented as shown below in this VHDL example. The not Q output is left internal to the latch and is not taken to an external pin. The not Q pin will always be at the opposite logic level as the Q pin.

S-R latch and symbol as implemented in VHDL

S-R Latch and Symbol as Implemented in the VHDL Code


How the S-R Latch Works

S and R Inputs Both Low

With both the S and R inputs at logic 0 level, the Q output will be latched at whatever value it was at. When at logic 0, the S and R inputs do not influence the output of the latch.

R Input Goes High and Low

When R goes high, the latch is reset – meaning that Q goes low. This assumes that S is low. If R goes low again, the output of the latch will remain latched low.

In other words, a positive pulse on R resets Q when S is low.

S Input Goes High and Low

With R low, when the S input goes high, the output of the latch will go high. If S is taken low after this, the Q output will remain latched high.

In other words, a positive pulse on S sets Q when R is low.

R and S Both High

R and S must never be allowed to go high at the same time. This is an undefined state for this type of latch.

S-R Latch Design in VHDL

Before reading further, take a few minutes to think how you would design this latch using the VHDL that you have learned so far on this course.

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Designing the Latch

Inputs and Outputs

The first thing to do would be to define the input and output pins:

entity S_R_latch_top is
    Port ( S : in  STD_LOGIC;
           R : in  STD_LOGIC;
           Q : out STD_LOGIC);
end S_R_latch_top;

S-R Latch Logic

Next, the logic needs to be designed using VHDL code. The not Q output will need to be defined as an internal signal as it is still part of the S-R latch, even though it was decided not to wire it to the outside of the latch. This signal will be added to the architecture part of the code.

architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin
-- the VHDL logic design of the S-R latch will go here
end Behavioral;

Let's take another look at the S-R latch and then design the logic.

S-R latch made from NOR gates, active high inputs

The Q output is made by NORing its two inputs. Its two inputs are R and the output of the second NOR gate – not Q. The VHDL code for the top NOR gate would then look like this.

Q <= R nor notQ;

The not Q output is made by NORing S and Q together. This is now added to the VHDL code.

notQ <= S nor Q;

The final VHDL code will now look like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity S_R_latch_top is
    Port ( S : in    STD_LOGIC;
           R : in    STD_LOGIC;
           Q : out   STD_LOGIC);
end S_R_latch_top;

architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin

Q    <= R nor notQ;
notQ <= S nor Q;

end Behavioral;

Synthesizing the VHDL S-R Latch

When the above code is synthesized, e.g. by using the Xilinx software tools, an error will be generated.

The error from the Xilinx tools states: Parameter Q of mode out can not be associated with a formal parameter of mode in.

This error is occurring because Q is an output and its value can't be read – i.e. it is read when NORing S and Q together to generate the notQ output.

Solving the Problem – Method 1

One way of solving this problem is to use another internal signal that will contain the value of Q. We will then be able to read this signal.

architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
signal Q2   : STD_LOGIC;  -- a copy of the Q output
begin

Q    <= R nor notQ;
Q2   <= R nor notQ;    -- a copy of Q
notQ <= S nor Q2;      -- use the copy of Q

end Behavioral;

The above logic can be further simplified by performing the NOR operation for the Q output only once:

Q    <= Q2;
Q2   <= R nor notQ;    -- a copy of Q
notQ <= S nor Q2;      -- use the copy of Q

Remember that the above statements are running concurrently, so it does not matter which order the statements are in.

The final VHDL code for this solution will now look like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity S_R_latch_top is
    Port ( S : in    STD_LOGIC;
           R : in    STD_LOGIC;
           Q : out   STD_LOGIC);
end S_R_latch_top;

architecture Behavioral of S_R_latch_top is
signal Q2   : STD_LOGIC;
signal notQ : STD_LOGIC;
begin

Q    <= Q2;
Q2   <= R nor notQ;
notQ <= S nor Q2;

end Behavioral;

Solving the Problem – Method 2

An even simpler method of solving this problem is to define the Q pin of type inout instead of out. This makes the Q pin readable within the VHDL code.

We can now take our original VHDL code and simply change out to inout:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity S_R_latch_top is
    Port ( S : in    STD_LOGIC;
           R : in    STD_LOGIC;
           Q : inout STD_LOGIC); -- changed out to inout
end S_R_latch_top;

architecture Behavioral of S_R_latch_top is
signal notQ : STD_LOGIC;
begin

Q    <= R nor notQ;
notQ <= S nor Q;

end Behavioral;




Source Code for Solutions

This source code is for the above two solutions to creating a S-R latch in VHDL. The VHDL, UCF and JED files are included. The UCF and JED files are configured for the home built CPLD board.

Solution 1: S_R_latch.zip (5.8kB)

Solution 2: S_R_latch_inout.zip (5.8kB)

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