Created on: 9 January 2013
This tutorial shows how to create a binary counter in VHDL. The counter is really only a modification of the clock divider from the previous tutorial.
The value of the eight-bit counter is shown on eight LEDs on the CPLD board.
This video shows the binary counter in operation.
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It is necessary to have a clock pulse supplied to the CPLD for this tutorial. This is supplied to pin P7 of the CPLD from the AVR on the home built CPLD board as described in tutorial 6.
The VHDL code listing for the binary counter is shown below.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binary_counter_top is Port ( CLK : in STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0)); end binary_counter_top; architecture Behavioral of binary_counter_top is signal CLK_DIV : std_logic_vector (2 downto 0); signal COUNT : std_logic_vector (7 downto 0); begin -- clock divider process (CLK) begin if (CLK'Event and CLK = '1') then CLK_DIV <= CLK_DIV + '1'; end if; end process; -- counter process (CLK_DIV(2)) begin if (CLK_DIV(2)'Event and CLK_DIV(2) = '1') then COUNT <= COUNT + '1'; end if; end process; -- display the count on the LEDs LED <= not COUNT; end Behavioral;
The VHDL source code with UCF and JED files can be downloaded here: VHDL-binary-counter.zip (6.2kB).
Again, note that the STD_LOGIC_UNSIGNED module of the IEEE library is necessary and is included with the use statement at the top of the file.
A clock divider, covered in the previous tutorial, has been used to provide a slower clock to the binary counter. This slow clock makes it possible to see the binary value counting up on the LEDs.
The binary counter is contained in a VHDL process with the input clock divided by 8 (CLK_DIV(2)) in its sensitivity list. This supplies a clock of about 16.25Hz when using an input clock of about 130Hz (as supplied by the AVR).
The binary counter works exactly the same way as the clock divider, but consists of eight bits.
The COUNT register contains the binary counter value and is incremented on every rising clock edge of the clock divider. The value of the COUNT register is displayed on the LEDs with the code LED <= not COUNT; which inverts the count value to compensate for the inverting LED outputs on the home built CPLD board.
The binary counter could also have been implemented using an 11-bit register and then connecting the top 8 bits of the register to the LEDs. This would then run the counter at the same speed as the above counter with clock divider.