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Tutorial 17: Forcing Logic State of Output Pins

Created on: 12 March 2013

The logic state of an output pin (logic 0 or logic 1) is forced onto the pin using VHDL. A fixed bit pattern is also put onto a set of output pins by forcing or fixing logic levels onto them using VHDL code.

This may be useful during VHDL development or to implement a fixed pattern on some pins that can be read by a microcontroller as DIP switch settings would be read. A different pattern on the pins can be used for the microcontroller to identify what VHDL code has been loaded to the CPLD or any other application where the microcontroller needs to read some fixed settings.

Setting the State of a Pin or Set of Pins

The VHDL to set the state of a pin or set of pins is simple as shown in the VHDL code listing below.

library IEEE;

entity fixed_output_top is
    Port ( OUT_1 : out  STD_LOGIC;
           OUT_4 : out  STD_LOGIC_VECTOR (3 downto 0));
end fixed_output_top;

architecture Behavioral of fixed_output_top is

    -- switch single output low (LED on)
    OUT_1 <= '0';
    -- write bit pattern to 4-bit wide output
    OUT_4 <= "0110";

end Behavioral;

Single Pin

For single output pins, the logic level is put onto the pin by specifying the logic level between single quotes. In the line of code below, a logic 0 will be put on the pin called OUT_1.

OUT_1 <= '0';

The above code will switch an LED on if OUT_1 is connected to an LED pin on the home made Xilinx CPLD board because the LEDs are wired in current sinking mode.

Multiple Pins

To write a bit pattern to a set of two or more pins, the logic levels or bit pattern to write is put between double quotes as shown in this line of code:

OUT_4 <= "0110";

This video shows the above VHDL code implemented on a CPLD.

Can't see the video? View on YouTube →

← Go back to VHDL Tutorial 16Go to VHDL Tutorial 18 →