Starting Electronics Needs Your Help!
It is that time of the year when we need to pay for web hosting and buy new components and equipment for new tutorials. You can help by making a donation. Contribute to this website by clicking the Donate button. The total will be updated once daily. (You may need to clear your browser cache to see the updates.)
Target Amount: $2000
Amount Raised: $1802.10
Top Donor: C.C. $100
Created on: 12 March 2013
The logic state of an output pin (logic 0 or logic 1) is forced onto the pin using VHDL. A fixed bit pattern is also put onto a set of output pins by forcing or fixing logic levels onto them using VHDL code.
This may be useful during VHDL development or to implement a fixed pattern on some pins that can be read by a microcontroller as DIP switch settings would be read. A different pattern on the pins can be used for the microcontroller to identify what VHDL code has been loaded to the CPLD or any other application where the microcontroller needs to read some fixed settings.
The VHDL to set the state of a pin or set of pins is simple as shown in the VHDL code listing below.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity fixed_output_top is Port ( OUT_1 : out STD_LOGIC; OUT_4 : out STD_LOGIC_VECTOR (3 downto 0)); end fixed_output_top; architecture Behavioral of fixed_output_top is begin -- switch single output low (LED on) OUT_1 <= '0'; -- write bit pattern to 4-bit wide output OUT_4 <= "0110"; end Behavioral;
For single output pins, the logic level is put onto the pin by specifying the logic level between single quotes. In the line of code below, a logic 0 will be put on the pin called OUT_1.
OUT_1 <= '0';
To write a bit pattern to a set of two or more pins, the logic levels or bit pattern to write is put between double quotes as shown in this line of code:
OUT_4 <= "0110";
This video shows the above VHDL code implemented on a CPLD.
Can't see the video? View on YouTube →