Starting Electronics Needs Your Help!
It is that time of the year when we need to pay for web hosting and buy new components and equipment for new tutorials. You can help by making a donation. Contribute to this website by clicking the Donate button. The total will be updated once daily. (You may need to clear your browser cache to see the updates.)
Target Amount: $2000
Amount Raised: $1224
Top Donor: C.C. $100
Created on: 12 March 2013
A single tri-state buffer with active low enable and a 4-bit wide tri-state buffer with single active low enable are written in VHDL code and implemented on a CPLD.
Both tri-state buffers are implemented in the same VHDL code of a single project.
This video shows the two tri-state buffers in operation on the home made Xilinx CPLD board.
Can't see the video? View on YouTube →
A single tri-state buffer with active low enable pin is shown below. A group of four tri-state buffers with a single enable pin is also shown. Both of these buffers are written in VHDL and implemented on a CPLD.
The VHDL code for the single and quad tri-state buffers is shown below.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tri_state_buffer_top is Port ( A : in STD_LOGIC; -- single buffer input EN : in STD_LOGIC; -- single buffer enable Y : out STD_LOGIC; -- single buffer output -- 4 input / output buffer with one enable IN4 : in STD_LOGIC_VECTOR (3 downto 0); EN4 : in STD_LOGIC; OUT4 : out STD_LOGIC_VECTOR (3 downto 0)); end tri_state_buffer_top; architecture Behavioral of tri_state_buffer_top is begin -- single active low enabled tri-state buffer Y <= A when (EN = '0') else 'Z'; -- 4 input/output active low enabled tri-state buffer OUT4 <= IN4 when (EN4 = '0') else "ZZZZ"; end Behavioral;
The single tri-state buffer is created in VHDL using the following line of code:
Y <= A when (EN = '0') else 'Z';
When the EN pin is low, then the logic level on the A input will appear on the Y output. If a logic 1 is on the EN pin, the output Y will be tri-stated (made high impedance indicated by Z in VHDL).
The quad input tri-state buffer with single enable is created with the following VHDL code:
OUT4 <= IN4 when (EN4 = '0') else "ZZZZ";
When the enable pin EN4 is low, then each of the logic states on the inputs of the buffers will appear on their corresponding outputs. If the EN pin has a logic high applied to it, then all buffers will be tri-stated ("ZZZZ" is used to tri-state all four buffers in the VHDL code).