Tutorial 1: VHDL Inverter and Buffer Code

Created on: 29 November 2012

This first tutorial in the VHDL course shows how to create an inverter in VHDL code that will invert the signal on a CPLD pin and connect the inverted signal to an output pin. It also shows how to create a buffer in VHDL that simply connects a signal on an input pin to an output pin of the CPLD.

Examples of how to create inverters and buffers on a single input and output pin as well as an input and output bus are used.

Various elements of the VHDL language are explained during the tutorial as they are used. You will learn the following in this tutorial:

  • What the basic elements of a VHDL project consist of
  • What library files are in VHDL
  • VHDL entity, architecture and file naming
  • Defining input and output ports
  • How to create an inverter and buffer
  • How to create and access a bus in VHDL

Making an Inverter in VHDL

An inverter is a logic gate that converts a logic level on its input to the opposite logic level on its output, i.e. a 0 on the input of an inverter will produce a 1 on its output; a 1 on the input of an inverter will produce a 0 in its output.

In this project, the push button on the Xilinx CPLD board is connected to the input of an inverter implemented in the CPLD that is written in VHDL code. The output of the inverter is connected to one of the LEDs on the CPLD board.

This video shows all of the VHDL code for this tutorial and what it does when run on the home made Xilinx CPLD board:

Can't see the video? View on YouTube →

Below is a listing of the VHDL code for the invert VHDL project and an explanation of various elements in the code. This is followed by information on how to create the project using the Xilinx tools.

The VHDL code for creating an inverter is as follows, this is the code from the invert_top.vhd file:

library IEEE;

entity invert_top is
    Port ( PB : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end invert_top;

architecture Behavioral of invert_top is
    -- invert the signal from the push button switch and route it to the LED
    LED <= not PB;
end Behavioral;

VHDL Elements

Library Files

invert_top.vhd contains the following statements at the top of the file:

library IEEE;

This includes the IEEE library in the VHDL design and specifies that all of the STD_LOGIC_1164 library package from the IEEE library will be used. You won't need to know much about libraries at this stage.

VHDL File and Entity Name

The entity describes the pins (or ports) used in the design:

entity invert_top is
    Port ( PB : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end invert_top;

The above statements define an input pin called PB (our push-button switch) and an output pin called LED (this will connect to one of the LEDs on the board).

The entity name in the VHDL file (invert_top.vhd in our example) has the same name as the VHDL file. In this example the entity name and file name are both invert_top.

The name invert_top was chosen for this project but could be named anything else. When a new VHDL file is added to the project in the Xilinx software, it will automatically create the entity code in the file and name it after the chosen file name.

VHDL files end with a .vhd file extension.

VHDL Architecture

The architecture describes the circuit functionality. This is where the actual logic design is written in VHDL:

architecture Behavioral of invert_top is
    -- invert the signal from the push button switch and route it to the LED
    LED <= not PB;
end Behavioral;

VHDL Comments

VHDL comments are started with two minus signs next to each other: --

Comments in the VHDL file are ignored by the software tools and allow the writer of the VHDL to include human readable comments and explanations in the VHDL file.

Semicolons and Case

Every VHDL statement must be terminated by a semicolon: ;

VHDL is not case sensitive so keywords and statements can be written in upper or lower case letters.

An Explanation of the VHDL Code

The actual VHDL code that describes the inverter is the single VHDL statement in the architecture part of the VHDL file:

LED <= not PB;

This statement basically says "Invert the PB input pin and put the inverted result on the LED pin. The schematic equivalent of this statement is shown below.

The schematic equivalent of the VHDL inverter code

Schematic of the VHDL Inverter Code

The above code inverts the logic level on the PB pin by using the VHDL not keyword. It then assigns the inverted logic level to the LED pin using the VHDL assignment operator <= which places the inverted value on the LED pin.

At this stage, the actual CPLD pin numbers used for PB and LED have not been defined. This VHDL code is now fully portable and can be moved to a different CPLD or FPGA. The actual pin numbers will be assigned to the pin names later.

Creating the Project using the Xilinx Software

Create the project by following the steps in the Starting a New Xilinx CPLD Project in ISE article, but make the following changes:

  1. Name the project invert.
  2. When the new source file (VHDL module) is added, name it invert_top.
  3. Specify the ports as PB - an input and LED - an output. Don't check the Bus checkbox during this step. This step can also be skipped and the ports defined manually in the VHDL file.
  4. Add the line of VHDL code to describe an inverter as already presented in the code listing above.
  5. Create a user constraints file and add the constraints described below.

Adding User Constraints

For the home made CPLD board, add constraints to assign PB to CPLD pin P3 and LED to CPLD pin P26 as shown in the figure below. This effectively connects the input of the inverter to pin 3 of the CPLD (the push button switch on the CPLD board) and the output of the converter to CPLD pin 26 (one of the 8 LEDs on the board). You could also assign one of the switches from the switch bank to the inverter input and any one of the other LEDs to the output of the inverter.

If you are using a different board, then you will need to check which input pin of the CPLD has a switch connected to it and which one has an LED connected to it and then assign the correct pins in the UCF file using Xilinx Pace.

CPLD pin assignment for the tutorial

CPLD Pin Assignment for the Inverter Tutorial - From the Xilinx Pace Software

Configuring the CPLD

Finish the project by generating the configuration file and then loading the configuration file to the CPLD.

Source Code

The VHDL file, UCF file and output JED file: invert-src-vhdl-ucf-jed.zip (5.8kB)

The entire Xilinx ISE 14 invert project: invert.zip (684.1kB)

Making a Buffer in VHDL

To make a buffer, which is the same as connecting and input pin to an output pin inside the CPLD, change the line of VHDL code to:

LED <= PB;

This just uses the VHDL signal assignment operator to connect the PB input to the LED output without inverting the input signal.

Inverting or Buffering a Bus in VHDL

The Starting a New Xilinx CPLD Project in ISE article uses VHDL code that implements an 8 bit bus that connects 8 switches to 8 LEDs.

The bus port pins are defined in the entity part of the VHDL code as follows:

Port ( SW  : in  STD_LOGIC_VECTOR (7 downto 0);
       LED : out STD_LOGIC_VECTOR (7 downto 0));

This code uses the STD_LOGIC_VECTOR type to define the buses and then specifies the size of the bus as 8 bits (7 down to 0).

The VHDL code for connecting the SW input bus to the LED output bus is shown below and connects all 8 bits of the buses in a single statement:

LED <= SW;

To invert each signal on the bus, in other words insert an inverter between each input and output on the bus, use the following VHDL statement:

LED <= not SW;

Don't forget to assign pin numbers in the user constraints file to all of the pins used in the bus.

Referencing Individual Signals on a Bus in VHDL

When port pins have been defined as being part of a bus, they can be individually used in the VHDL code as follows:

LED(3) <= SW(5);

This line of code connects the bus line connected to switch 5 of the switch bank to LED 3 of the set of 8 LEDs on the CPLD board (provided that they are defined that way in the UCF file).



← Go back to Introduction to VHDL and CPLD DevicesGo to VHDL Tutorial 2 →